![]() In order to synchronize multi bit signal using 2 flip flop synchronizer method, only a single bit change must be guaranteed at a particular clock cycle. So output of every synchronizer may not settle to correct value at same clock. Metastability can cause a flip flop to settle down either to a true value or a false value. When multi bit signals are synchronized with 2 flip flop synchronizer, each bit is synchronized using separate 2-FF synchronizer. Thus the logic generating the pulse shall not generate another pulse till the busy signal is asserted.įigure 5 Handshake based pulse synchronizerįigure 6 Timing for handshake based pulse synchronizer Gray encoding for multi bits signal To make sure the next generated pulse in source clock domain gets definitely transferred and synchronized in the destination clock domain, the handshake based pulse synchronizer generates a “Busy” signal by ORing A1 and A3 flip-flop outputs. There is one restriction in pulse synchronizer that back to back (one clock gap) pulses cannot be handled. In handshake based pulse synchronizer, as shown in Figure 5 and Figure 6, synchronization of a pulse generated into source clock domain is guaranteed into destination clock domain by providing an acknowledgement. Diagram in Figure 3 and Figure 4 shows toggle synchronizer implementation and Timing diagram.įigure 4 Timing for toggle synchronizer Pulse synchronizer While synchronizing from fast clock domain to slow clock domain using 2 FF synchronizer, the pulse can be skipped which can cause the loss of pulse detection & hence subsequent circuit which depends upon it, may not function properly. ![]() ![]() A pulse cannot be synchronized directly using 2 FF synchronizer. Toggle synchronizer is used to synchronize a pulse generating in source clock domain to destination clock domain. Output of flop B2 can go to metastable if B1 does not settle to stable value during one clock cycle, but probability for B2 to be metastable for a complete destination clock cycle is very close to zero.Ī greater number of flop stages may be used if frequency is too high as it will help in reducing the probability of synchronizer output to remain in metastable state.įigure 2 Timing for conventional 2FF synchronizer Toggle synchronizer But during the one clock cycle period of CLK_B clock, output B1-q may settle to some stable value. There is probability that while sampling the input B1-d by flip flop B1 in CLK_B clock domain, output B1-q may go into metastable state. As shown in Figure 1 and Figure 2, flip flop A and B1 are operating in asynchronous clock domain. In general, a conventional two flip-flop synchronizer (2-FF) is used for synchronizing a single bit level signal. Let us begin with the most common and simple option. This week we will look at standard synchronization techniques for multi-clock domain SoCs and FPGAs. ![]()
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